The present invention relates to a power source circuit device used for a semiconductor memory such as a flash memory, an EEPROM, or the like.
FIG. 1 shows a structure of a conventional power source circuit used for a flash memory, in which an external power source VPP of, for example, 12V used for writing and erasing data on a memory cell is provided in addition to a VDD power source (not shown) used for normal reading operation.
A reference potential generation circuit VREF 5 generates a reference potential and supplies the potential to input terminals of a stepdown circuit WL Reg. 3 and a stepdown circuit PBL Reg. 4.
The input terminal of the stepdown circuit 3 is supplied with output potentials of the high voltage power source potential VPP and the reference potential generation circuit VREF 5. An output of the stepdown circuit 3 is supplied to an input terminal of a power source switch circuit WL SW 6.
The stepdown circuit 3 directly outputs a high voltage power source potential VPP without lowering this power source potential VPP when writing or erasing data on a memory cell 15. When verification is performed, the high voltage power source potential VPP is stepped down to, for example, 6V which is outputted.
The input terminal of the power source switch circuit 6 is supplied with the output potential of the stepdown circuit 3 and the power source potential VDD, and the output terminal of the circuit 6 is connected to the power source terminal VWL of the row decoder circuit 10.
The power source switch circuit 6 selects and outputs either one of the output potential or the power source potential VDD in accordance with the state of the memory cell 15, i.e., the state in which data is written, the state in which data is erased, or the state in which data is verified.
The row decoder circuit 10 supplies a potential supplied from the power source switch circuit 6, to a selected word line.
In addition, the power source terminal of a cell source decoder circuit 9 is supplied with a high voltage potential VPP. The cell source decoder circuit 9 supplies a high voltage source potential VPP to a source of the memory cell 15 when erasing data on the memory cell 15.
Further, an input terminal of a power source switch circuit Col. SW 7 is supplied with a high voltage power source potential VPP and a power source potential VDD (not shown), while an output terminal of the power source switch circuit Col. SW 7 is connected with a power source terminal VCOL of a column decoder circuit 11. The power source switch circuit Col. SW 7 selects and outputs either a high-voltage power source potential VPP or a power source potential VDD in accordance with the state of the memory cell 15, i.e., the state in which data is written into the memory cell 15, the state in which data is erased therefrom, or the state in which data is read therefrom or the state in which data is verified.
In addition, an output terminal of the column decoder circuit 11 is connected to a gate of a column select transistor 14 and outputs a potential to be supplied to the power source terminal VCOL of the column decoder circuit 11.
In addition, an input terminal of a stepdown circuit PBL Reg. 4 is supplied with a high-voltage power source potential VPP and an output potential of a reference potential generation circuit 5. The stepdown circuit 4 steps down a high voltage power source potential VPP to generate a potential of, for example, 8.5V to be applied to a gate of a write transistor 13 when writing data into a cell, and the stepdown circuit 4 supplies the potential to an input terminal of the power source switch circuit PBL SW 8.
The input terminal of the power source switch circuit 8 is supplied with an output potential VPB of the stepdown circuit 4 and the power source potential VDD. An output terminal of the power source switch circuit 8 is connected to a power source terminal VPBL of a write transistor decoder circuit 12. The power source switch circuit 8 selects and outputs either an output potential of the stepdown circuit 4 or an external power source potential VDD, in accordance with the state of the memory cell, i.e., the state in which data is written into the memory cell, the state in which data is erased therefrom, or the state in which data is read therefrom.
The write transistor decoder circuit 12 outputs a potential supplied from the power source switch circuit 8, to a gate of the write transistor 13.
In addition, a drain of the write transistor 13 is supplied with a high voltage power source potential VPP.
In a power source circuit used in a non-volatile semiconductor memory such as a conventional flash memory as described above, it is necessary to prepare an external high voltage power source VPP for a high potential to be used for writing and erasing, in addition to a power source VDD used for normal reading operation. Therefore, there is a problem that costs must be raised, and therefore, developments in a power source circuit device which is capable of reading or verifying data on a memory cell without using an external high voltage power source VPP have been waited for.
U.S. Pat. No. 5,077,691 discloses a structure from which an external high-voltage power source is omitted and in which an external high-voltage power source connected to a memory cell is replaced with a charge pump. However, this structure is limited to a case where data is erased with a negative gate voltage, and therefore, the memory cell itself must be improved in order to maintain a constant erasing characteristic and a retaining characteristic of data processing of the memory cell.